FIG. 1 illustrates a conventional vertical double-diffused MOSFET (DMOS) 10 with a trench gate 11, a diffused P-type body diffusion (PB), a shallow N+ source region 12, a P+ body contact region 13, formed in an N-type epitaxial layer Nepi grown on an N+ substrate. A source metal 14, using a butting contact structure, shorts the source and body contact regions 12 and 13. The gate 11 is embedded in a trench 15 etched into the epitaxial layer Nepi, oxidized and then filled with doped polysilicon. The channel of the device is formed along the sidewall of the trench in the silicon region extending between the N+ source-to-PB body junction to the junction formed between the PB body and the N-type epitaxial drain. In conventional devices, the gate oxide 16 on the trench sidewalls and bottom is formed simultaneously and is therefore of uniform thickness (except for the subtle variations due to compressive oxidation effects on curved surfaces and differing oxidizing rates on various crystallographic planes).
The drain doping is typically lower in concentration than the PB body region so as to provide substantial depletion spreading in the drain and minimal depletion spreading in the channel for any applicable voltage. The heavier doping in the PB body avoids punchthrough breakdown and other undesirable effects of the short channel, which normally has an effective length of 0.3 to 1 μm.
The on-resistance of such a device is determined by the sum of its resistive components shown in FIG. 2, namely its substrate resistance (Rsub), its epitaxial drain resistance (Repi), its channel resistance (Rch), its source contact resistance (Rc), and its metal interconnect resistance (RM). The epitaxial resistance (Repi) is subdivided between a region where current emanating from the channel is spreading out (Repi1) and, in the case of thicker epitaxial layers, another region where the current has become uniform (Repi2).RDS=RM+Rc+Rch+Repi+Rsub  (1)whereRepi=Repi1+Repi2  (2)
The primary design goal for a power MOSFET used as a switch is to achieve the lowest on-resistance by simultaneously minimizing each of its resistive constituents. The following factors must be considered:
1. The metal resistance is minimized through the use of a thicker metal layer.
2. Grinding the wafer to the thinnest possible dimension minimizes the substrate resistance. The grinding must be performed near the end of the fabrication process so that the risk of breakage from handling is minimized.
3. There is an unavoidable tradeoff between the avalanche breakdown voltage and the on-resistance of the device. Higher breakdown voltages require thicker, more lightly doped epitaxial layers contributing higher epitaxial resistances. Generally, the doping of the epitaxial layer is chosen so as to provide the most highly-doped layer capable of supporting the required off-state blocking voltage (i.e., its specified avalanche breakdown voltage).
4. The channel resistance is minimized by maximizing the channel perimeter for a given area. The individual cells of the MOSFET may be constructed in any striped or polygonal shape. Ideally, the shape chosen should be one that can be repeated at a regular pitch so that more cells can be connected in parallel in a given area. Paralleling many cells and operating them in tandem can achieve an extremely low on-resistance.
5. Higher cell densities have the advantage that the current in the epitaxial drain becomes uniform closer to the surface, more fully utilizing the epitaxial layer for conduction and reducing the spreading resistance term (Repi1) of the epitaxial resistance. As may be seen be by comparing FIG. 3A with FIG. 3B, a smaller cell pitch reduces the area wasted where no current flows, conducting current uniformly through a greater percentage of the total thickness of the epitaxial layer. The more uniform conducting epitaxial layer exhibits a lower drain resistance.
Maximizing the perimeter of the trench gate for a given area lowers the channel resistance (Rch), since the equation for the MOSFET channel conduction depends on the total “perimeter” of the gate, not the area of the device.
The equation for the channel resistance of a conventional lateral MOSFET can be used to approximate the channel resistance of a vertical DMOS.                                           R            ch                    =                      1                          μ              ·                              C                ox                            ·                              W                                  L                  ch                                            ·                              (                                                      V                    GS                                    -                                      V                    t                                                  )                                                    ⁢                                  ⁢        where                            (        3        )                                                      C            ox                    =                                    ɛ              ox                                      χ              ox                                      ⁢                                  ⁢                  combining          ·          gives                                    (        4        )                                                      R            ch                    ·          W                =                  1                      μ            ·                          C              ox                        ·                          1                              L                ch                                      ·                          (                                                V                  GS                                -                                  V                  t                                            )                                                          (        5        )            
Expressed in terms of area using the geometric figure of merit A/W yields the form                                                         R              ch                        ⁢            A                    =                                    R              ch                        ⁢                          W              ·                              A                W                                                    ⁢                                  ⁢        whereby                            (        6        )                                                      R            ch                    ⁢          A                =                              1                          μ              ·                              C                ox                            ·                              1                                  L                  ch                                            ·                              (                                                      V                    GS                                    -                                      V                    t                                                  )                                              ·                      A            W                                              (        7        )            
Since it is desirable to maximize W and minimize A, the figure of merit A/W needs to be reduced to lower the channel resistance. To determine the A/W for various cell geometries, the equations for area A and perimeter W can be defined in terms of the trench width (the surface dimension YG of the trench, as distinguished from the “gate width W”) and the width YSB of the source-body “mesa” between trenches. For the continuous stripe of surface length Z, as shown in FIG. 4A, we haveA=Z·(YG+YSB)  (8)andW=2Z  (9)yielding                               A          W                =                              (                                          Y                G                            +                              Y                SB                                      )                    2                                    (        10        )            
In other words, the A/W for a stripe geometry is simply one-half of the pitch. For the square cell of FIG. 4B, the perimeter isA=(YG+YSB)2  (11)andW=4YSB  (12)so                               A          W                =                                            (                                                Y                  G                                +                                  Y                  SB                                            )                        2                                4            ⁢                          Y              SB                                                          (        13        )            
Compared to the stripe geometry, the square cell geometry offers a lower resistance whenever the gate is small compared to the source-body dimension. Since in a conventional trench-gated DMOS, manufacturing a small trench is not as difficult as manufacturing a small silicon mesa, the closed cell geometry is superior in performance. In the event that the gate dimension is larger than the source-body mesa dimension, the stripe geometry offers superior performance. This circumstance is difficult to achieve in practice, especially in narrow trench gate designs where the alignment tolerances needed to form the source and body regions and to establish a contact to them leads to a wide mesa. Whenever the gate dimension YG and the source-body mesa dimension YSB are equal, there is no difference between the two geometries in terms of minimizing A/W.
The presence of a source at the square corners in an array of trench-gated DMOS cells has been found to lead to off-state leakage in the device, possibly due to defects along the trench corners or some enhanced diffusion of the source along the corners. One solution to this problem is to block the N+ source from being implanted into the corners of the trench using a photoresist mask, as shown in FIG. 4C. Unfortunately, this corner block feature reduces the gate perimeter of the device and increases channel resistance. Assume the donut-shaped source has a width of YS, which necessarily must be less than half the mesa width YSB. If we remove only the corners from the source mask as shown, the perimeter of the device is no longer 4YSB, but drops toW=4·(YSB−YS)  (14)so                               A          W                =                                            (                                                Y                  SB                                +                                  Y                  G                                            )                        2                                4            ·                          (                                                Y                  SB                                -                                  Y                  S                                            )                                                          (        15        )            
The predicted resistance penalty due to the corner block is linear, so if YS is 20% of YSB, the gate perimeter is reduced by 20% and the channel resistance is increased accordingly. This explanation is a worst-case model since it assumes no conduction in the corner-blocked region. In reality, some current flows in the corner blocked regions, but they correspond to a transistor having a longer channel length and possibly a different threshold voltage. Furthermore, as the cell is scaled to smaller dimensions it becomes impractical to continue to employ the corner block concept since the corners become too close together. The reduction of source perimeter becomes substantial in such a case and the contact area of the source also suffers.
The need for corner blocking may conceivably be eliminated in a hexagonal cell trench DMOS (see FIG. 4D), since the angles around the perimeter of the hexagonal mesas are less acute (actually obtuse). On the other hand, the etched surfaces of the trench do not run parallel to natural crystallographic planes in silicon. By cutting across multiple crystal surfaces, the surface roughness of the channel is increased, channel mobility declines, and channel resistance increases. Despite some claims to the contrary in commercial and industry trade magazines, the packing density of hexagonal cells is no better then the conventional square cell design, resulting in exactly the same A/W.
Thus, to maximize the cell density and minimize the cell pitch of a vertical trench-gated DMOS, the trench gate surface dimension and the surface dimension of the mesa should both be minimized as long as A/W is reduced. The minimum possible trench dimension is a function of the trench etch equipment, the trench width and depth, the shape of the trench including rounding, and the trench refill process. Despite all these variations, the minimum drawn feature size of the trench is a single layer dimension, i.e., its minimum feature size is determined by the wafer fab's ability to print, etch and fill a trench, not by some interaction to other photomasking layers. The minimum trench size is then specified as a single layer mask feature. A single mask layer design feature is commonly referred to as a single layer dimension or SLD. As photomasking equipment now used exclusively for microprocessor and DRAM manufacturing becomes available for power semiconductor production, the trench width SLD is likely to shrink.
The minimum dimension of the source-body mesa is determined by the design rules associated with more than one photomasking layer, i.e., it involves multi-layer dimensions (MLD) design rules. The rules account for variability both in a critical dimension (referred to as ΔCD) and registration error of one masking layer to another, known as overlay or OL. ΔCD variations in a feature size are a consequence of variability in photoresist thickness and viscosity, exposure time, optical reflections, photoresist erosion during etching, etching time, etch rates, and so on. The variability due to OL layer-to-layer misalignment is more substantial.
FIGS. 5A-5E illustrate the components of variability in setting the minimum size of the trench DMOS mesa. In this case the mesa width is set by three design rules.
1. Minimum space of contact to trench. The purpose of the design rule illustrated in FIG. 5A is to prevent the metal contact from shorting to the gate (see catastrophic failure shown in FIG. 5D). Assuming that the contact is aligned to the trench, OL represents a single overlay misalignment. ΔCD1 represents the variation in the width of the trench width, while ΔCD2 represents the variation in the contact size. The values for ΔCD1 and ΔCD2 are divided by two for the half cells. The minimum space considering all variation must exceed zero to prevent a short between the embedded gate polysilicon and the source metal.                               DR                      cntct            /            trench                          ≥                              OL                          1              ⁢              misalignment                                +                                    Δ              ⁢                                                           ⁢                              CD                1                                      2                    +                                    Δ              ⁢                                                           ⁢                              CD                2                                      2                                              (        16        )            
2. Minimum overlap of metal contact and N+ source. The purpose of the design rule illustrated in FIG. 5B is to guarantee contact between the metal contact layer and the N+ source (see FIG. 5E for an example of misalignment). Assuming that the contact mask is aligned to the trench feature on the wafer, OL represents at least two successive misalignments, i.e., one misalignment can occur in aligning the contact mask to the trench, and a second (statistically independent) misalignment can occur between the N+ source mask and the trench. ΔCD3 represents the variation in the width of the N+ source region while ΔCD2 represents the variation in the size of the contact (to metal). The minimum space per side considering all variations must exceed a net overlap δN+ to guarantee an ohmic contact between the metal contact and the N+ source region.                               DR                      N            +                          ≥                              OL                          2              ⁢              misalignments                                +                                    Δ              ⁢                                                           ⁢                              CD                3                                      2                    +                                    Δ              ⁢                                                           ⁢                              CD                2                                      2                    +                      δ                          N              +                                                          (        17        )            
3. Minimum contact between P+ body contact region and metal contact. The purpose of the design rule illustrated in FIG. 5C is to guarantee ohmic contact between the metal contact and the P+ body contact region by insuring that the N+ source region does not completely cover the P+ body contact region. ΔCD3 is the variation in the width of the N+ source region. Since the total size of the opening through the N+ source region can shrink by ΔCD/2 on each side, a total possible variation in size is ΔCD. The minimum space considering all variation must exceed a net overlap δP+ to guarantee an ohmic contact between the metal contact and the P+ body contact region. In the extreme case, shown in FIG. 5F, the entire P+ region is covered by the lateral extensions of the N+ regions, overlapping at the center of the cell. For the half cell,DRP+≧ΔCD3+δP+  (18)
In conclusion, the minimum mesa width, then, is determined by two contact-to-trench rules (one on each side of the mesa), two N+ contact rules (to guarantee contact to the N+ source on both sides of the mesa), and a single P+ rule. But since a misalignment in the contact mask toward one trench increases the distance to the other, each design rule must be considered only once when calculating the minimum mesa dimension. Assuming all OL and ΔCD rules, the minimum width of the mesa is:YSB(min·mesa)=3ΔCD+3OL+2δN++δP+  (19)
For example, assuming a ±3-sigma OL error of 0.25 μm, a 3-sigma ΔCD of 0.1 μm, a minimum N+ overlap of 0.1 μm (for each N+ as drawn), and a minimum N+ opening (to contact the P+) of 0.3 μm, the minimum source-body mesa size is:                                                                                           Y                  SB                                ⁡                                  (                                      min                    ·                    mesa                                    )                                            =                                                3                  ⁢                                      (                    0.1                    )                                                  +                                  3                  ⁢                                      (                    0.25                    )                                                  +                                  2                  ⁢                                      (                    0.15                    )                                                  +                0.65                                                                                        =              2.0                                                          (        20        )            
In practice, however, an additional 0.5 μm may be needed to achieve high yields, good defect tolerance, and improved P+ contact areas. Below this 2 μm mesa, it becomes difficult to implement a trench DMOS using a contact mask and a butting N+/P+ source-body contact. In such a case, a design wherein the N+ source region extends from trench-to-trench across the silicon mesa must be used. The P+ body contact used to connect to the underlying PB body diffusion can be contacted in the z-dimension (along the length of the stripe). Two contact-to-trench features and the contact dimension then determine the mesa width.YSB(min·mesa)=2ΔCD+2OL+δN+  (21)which, applying the same tolerances but with a 0.4 μm N+ contact window, yields                                                                                           Y                  SB                                ⁡                                  (                                      min                    ·                    mesa                                    )                                            =                                                2                  ⁢                                      (                    0.1                    )                                                  +                                  2                  ⁢                                      (                    0.25                    )                                                  +                0.4                                                                                        =              1.1                                                          (        22        )            
In practice, to achieve high yields and good defect tolerance, larger dimensions are likely required, as large as 1.5 μm. Below a mesa width of around 0.9 to 1.1 μm, even fine line contacts and accurate layer-to-layer alignments become difficult. Moreover, at these dimensions, other manufacturing-related problems exist.
Another design and process consideration in a trench-gated DMOS is the resistance of the body region PB and the quality of the body contact shorting it to the source metal. The source-to-body short prevents conduction and snapback breakdown of the parasitic NPN bipolar transistor (see the cross-sectional view of FIG. 7A) by maintaining the emitter and base at the same potential. Shorting the emitter and base terminals ideally prevents forward-biasing of the emitter-base junction and avoids consequent minority carrier (electron) injection into the MOSFET's body (i.e., base).
The frequency of the body pickup determines the base resistance along the z-direction. In a “ladder” design, the P+ body contact regions occasionally interrupt the N+ source stripe to pick up the body region electrically. (See the plan view of FIG. 7B and the three-dimensional projection view of FIG. 7C). The “pinch resistance” of the portion of the P-body region PB that lies under the N+ source region must be maintained at a low value without adversely affecting other device characteristics such as the threshold voltage. The method used to form the P-body region and the integration of a shallow P+ region used to achieve a low resistance ohmic contact to the body, are specific to each trench-gated DMOS design and process. Many commercial power MOSFETs today are inadequate in this regard and suffer from snapback and ruggedness problems as a result. The smaller or less frequent the P+ contact, the more likely snapback will occur.
Whenever a small contact feature is used to achieve a small mesa and high cell density, another problem occurs with respect to the step coverage of the metal contact. As shown in FIG. 8A, the deposition via sputtering of the top metal such as aluminum-silicon, aluminum-copper, or aluminum-copper-silicon, follows the contact shape conformally, leading to a notch or gap in the middle of the metal layer 70. The notch is not too severe in the case of a thin metal layer. But the resistance of a thin metal layer, especially under 1.2 μm thick, is too high to be useful in a power device. Surface metal resistance can add milliohms of resistance to a trench-gated DMOS laterally (as current flows along the surface of the device to the bond wire or source pickup), producing a significant fractional increase in the on-resistance of a large die product. A thick metal layer (e.g., 3 to 4 μm in thickness) is needed to minimize the on-resistance problem. However, as shown in FIG. 8B, thick metal layer 72 exhibits extreme notching, which results in thin metal at the contact step caused by the oxide layer 71. Since all of the current must flow through the thin metal and over the step, the device still exhibits high metal resistance and also suffers from poor electromigration performance, despite the thick metal deposition.
The oxide step height in the active contact area can be reduced by depositing a thinner interlayer dielectric (ILD), but the thinner dielectric may exhibit metal breakage wherever metal runs over the polysilicon gate bus. The thinner ILD also can cause shorts between the source metal and the polysilicon gate bus or lead to a thin oxide sensitive to ESD damage. As an example, FIG. 9A shows a metal layer 90 crossing over a gate bus 92. The metal step coverage problem occurs anywhere in the die where the source metal crosses the polysilicon gate bus, because the surface polysilicon is too thick. It occurs because the polysilicon gate bus sitting on the die surface has a thickness resulting from the polysilicon planarization of the trench. This thickness of the polysilicon must be thick enough to fill the trench at its widest point. Assuming a 1-um wide trench, the widest point occurs at the trench corner on the diagonal, with a dimension of around 1.4 μm (see FIG. 9B). The thickness of the polysilicon above the surface of the die after deposition needs to be at least half the dimension of the diagonal to fill the trench, as shown in FIG. 9C, to ensure that the polysilicon does not dip below the die surface later during etchback. This entire polysilicon thickness, in the example case 0.7 μm, plus an underlying oxide will be present on top of the die in the gate bus, so a 1 to 1.5 μm step is likely. The area of the gate bus is normally masked during the planarization etchback of the polysilicon, resulting in the step. The thick polysilicon also limits the possible manufacturing process sequence because the polysilicon is too thick to introduce dopants through it.
To summarize, one problem with existing conventional trench-gated vertical DMOS devices is that the cell density cannot be increased and the geometric-area-to-gate-perimeter ratio cannot be further reduced to produce improvements in the area efficiency of low-on-resistance switches, since the construction of conventional trench-gated vertical DMOS imposes fundamental restrictions in cell dimensions. The resistance penalty is especially significant for low voltage devices where a large portion of the total resistance is attributable to the resistance of the MOS channel (Rch). The limitations on cell density are primarily a consequence of the minimum width of the mesa between trenches. The minimum width of the mesa is determined by the use of multiple mask layers and is especially due to the design rules associated with the contact mask.
Stripe geometries reduce or eliminate the need for frequent or large area abutting source/body shorts, allowing tighter cell pitches but potentially creating problems in achieving good breakdown and snapback characteristics. Pushing the minimum possible contact dimension requires a solution to the metal step coverage problem in the active contact areas and over the gate bus. But without pushing the design rules to the point where the width of the mesa equals the width of the gate trench, the A/W of the stripe geometry is inferior to the A/W of a square cell geometry having a similar cell pitch.